The present invention relates to a semiconductor memory device and a memory system using the same and, more particularly, to a redundancy system and method for remedying a failure.
More specifically, the present invention relates to an address identification system and method for identifying an address having undergone spare replacement in a multi-bit memory or the like for inputting/outputting data parallel.
For a large memory capacity, it is becoming important to simultaneously exchange a plurality of data with the memory upon reception of an address in order to effectively utilize the capacity. That is, the memory must have a multi-bit arrangement.
As the data amount which can be simultaneously exchanged increases, the data transfer efficiency increases to effectively utilize the capacity of the memory serving as a high-speed data transfer memory. At this time, the address spaces of bits simultaneously transferred are the same, and cannot be externally discriminated by addresses. In other words, the addresses of simultaneously input/output data are completely the same, and identified by only different I/Os outside the memory.
If the capacity of the memory becomes larger, the memory is manufactured by an advanced micropatterning technique. The non-defective ratio of memories as products, i.e., the yield greatly depends on the presence of dust and particles in the manufacturing process, the fluctuation of the manufacturing process, or the like.
Accordingly, the ratio of non-defectives in which all memory cells serving as data storage locations are perfect is naturally low. For this reason, the yield must be increased by a redundancy technique of arranging a redundancy memory cell in advance in addition to a memory cell having an originally necessary capacity, replacing a memory cell in which a failure occurs with the redundancy memory cell, and remedying the failure-memory cell.
FIG. 1 is a block diagram showing a conventional multi-bit memory. Memory cell arrays 11-1 to 11-n in which memory cells are laid out in an array have row decoders 12-1 to 12-n, sense amplifiers 13-1 to 13-n, and column switches 14-1 to 14-n, respectively.
When a row address signal is supplied to the row decoders 12-1 to 12-n, data of memory cells on selected rows in the memory cell arrays 11-1 to 11-n are sensed, amplified, and then latched by the sense amplifiers 13-1 to 13-n.
The sense amplifiers 13-1 to 13-n are commonly the memory to select a column, this column address signal is used to specify a failure-column and replace it with a spare column.
DQ lines common to the memory cell arrays 11-1 to 11-n are called over-laid DQ lines 15a. The respective pairs of over-laid DQ line 15a are selectively connected to sense amplifier circuits 13a each having four sense amplifiers via column switches 14a.
Eight pairs of over-laid DQ lines 15a have one pair of square DQ lines 15b. The spare DQ lines 15b are connected to a spare sense amplifier circuit 13b having four spare amplifiers via a spare column switch 14b.
If a failure-column belongs to any one of the eight pairs of DQ lines 15a, the pair of DQ lines are entirely replaced with the pair of spare DQ lines 15b. The eight pairs of DQ lines 15a and one pair of spare DQ lines 15b belong to one I/O, and are selectively connected to each of the DQ buffers 17-1, 17-2, . . . via a corresponding one of DQ decoders 16-1, 16-2, . . . .
The DQ buffers 17-1, 17-2, . . . are respectively connected to RWD (read/write/data) buses 18-1, 18-2, . . . to output/input I/O data outside the memory.
A fuse box 19 is constituted by a 4-bit circuit, i.e., a 1-bit fuse circuit 19a representing whether the spare DQ lines 15b are used, and 3-bit fuse circuits 19b, 19c, and 19d representing a failure-one of the eight pairs of over-laid DQ lines 15a.
The address of the failure-DQ line is designated in the fuse circuits 19b, 19c, and 19d. When the bits of a column address signal corresponding to the failure-DQ line coincide with the three bits, the DQ decoders 16-1, 16-2, . . . are switched to select the spare DQ lines 15b.
In general, each of the fuse circuits 19a to 19d constituting the fuse bits has a fuse element, which is fused and programmed by a current, a laser beam, or the like.
In the above arrangement, however, even when a spare must be used at only one I/O, the lines having the same address are also replaced with spares at all other I/Os.
No problem arises when the number of I/Os is small, and the number of DQ lines belonging to one I/O is large. However, as the number of bits increases, the number of spares increases, and spares are unnecessarily replaced simultaneously. For this reason, the above-described multi-bit memory redundancy system and method are wasteful.
In various systems using a semiconductor memory device with the above arrangement, when a failure occurs in a memory cell due to a deterioration over time or the like, the redundancy technique cannot be applied upon incorporating the memory device into the system.
As described above, the conventional semiconductor memory device in inefficient for failure remedy.
The redundancy system and method in the conventional multi-bit memory are wasteful and inefficient.
By the address identification system and method in the conventional multi-bit memory, an address in the multi-bit memory cannot be identified for each I/O, and spare replacement is inefficient.
In the conventional memory system and its redundancy method, when a failure occurs in a memory cell due to a deterioration over time or the like, the redundancy technique cannot be applied upon incorporating the memory cell into the system, and the failure of the memory cell becomes the failure of the whole system.